A Feed Forward Equalization Transmitter Architecture which Is Robust to Coefficient Errors for High-Speed Wireline Communication
This talk will present a feed forward equalization (FFE) transmitter (TX) architecture which is robust to coefficient errors and improves power efficiency. As data rate and channel loss increase in wireline communication, the accuracy requirements for FFE coefficients and digital-to-analog converters (DACs) of the TX increase. To relieve such requirements, the transmitter to be presented utilizes the channel loss to attenuate the effects of the coefficient errors on the received signal. In addition, by removing current subtraction, power efficiency is improved. In experiment, the effect of errors and power efficiency are improved by 230% at 25dB and by 230%, respectively.