Digital Post-Correction of Nonlinearity with Memory Effects in GaN HEMT Track-and-Hold Circuits for High Performance ADCs

This talk presents the recent development of GaN HEMT track-and-hold sampling circuits (THSCs) with a digital post-correction (DPC) technique for high-performance ADCs in wireline communication as well as for other emerging applications. Compared to THSCs in Si/SiGe/GaAs/InP technologies, GaN THSCs achieve 20–30 dB higher signal-to-noise ratio (SNR) for a given bandwidth. Nevertheless, GaN THSCs suffer from dynamic nonlinearity due to charge trapping and introduce low-frequency dispersion, thus providing no more than 40–50 dB spurious-free dynamic range (SFDR). Conventional DPC techniques have been used to linearize CMOS data converters with weak memory effects, and thus cannot achieve sufficient dynamic nonlinearity correction on GaN HEMT THSCs with deep memory effects. In order to provide dynamic nonlinearity correction on GaN HEMT THSCs for Nyquist bandwidth, a DPC technique based on a truncated Volterra series will be discussed.