A Digital PLL Architecture with Digital-Signal-Processing Techniques for Spur Mitigation
Digital phase-locked loops (DPLLs) have attracted increasing attention due to its flexibility for frequency synthesis as well as scalability and portability with technology. One critical design challenge is the associated spur issue. For instance, spurs can cause unwanted reciprocal mixing or violate emission mask when used in a wireless transceiver. The spurious tones can be generated externally or internally. In a modern system-on-chip (SoC) platform, there will be many noisy aggressors such as baseband digital processors, clock buffers from other domains, or simply other PLLs. Those aggressors may cause the phase disturbance of the reference buffer or DCO depending on the coupling medium, which is often unpredictable and hard to be pre-calculated. On the other hand, the internal spur originates due to the PLL fractional-N operation, which will introduce a sawtooth-like phase disturbance. Moreover, the DNL effect of the TDC inside DPLL can worsen this spur error pattern, making the spur cancellation more difficult. In this presentation, the speaker will present a DSP-enabled DPLL architecture leveraging adaptive filter techniques to address aforementioned internal and external spur issues.