Model Order Reduction Techniques for Digital Predistortion in Highly Efficient Power Amplification Architectures
Digital predistortion (DPD) linearization is the most common and spread solution to cope with power amplifiers (PA) inherent linearity versus efficiency trade-off. The use of 5G spectrally efficient signals with high peak-to-average power ratios (PAPR) occupying wider bandwidths only aggravates such compromise. When considering wide bandwidth signals, carrier aggregation or multi-band configurations in high efficient transmitter architectures, such as Doherty PAs, envelope tracking PAs or outphasing transmitters, the number of parameters required in the DPD model to compensate for both nonlinearities and memory effects can be unacceptably high. This has a negative impact in the DPD model extraction/adaptation, because increases the computational complexity and drives to over-fitting and uncertainty. However, by applying regularization techniques we can both avoid the numerical ill-conditioning of the estimation and reduce the number of coefficients of the DPD function, which ultimately impacts the baseband processing computational complexity and power consumption. Therefore this talk will present an overview on several model order reduction techniques applied to enhance the robustness and performance of the DPD linearizer.