An Ultra-Low Power Dual-Core ARM®-Based Wireless MCU in 40 nm RF-NV CMOS for Battery Supplied IoT Applications
This presentation focuses on the different techniques used to reach state of the art power figures out of a leaky 40 nm process node, in an 8.6 mm² ultra-low power wireless dual-core ARM®-based microcontroller with 640 KB embedded Flash memory, 152 KB SRAM and 22 I/Os. Active current consumption is minimized by supplying the circuit through an integrated 85% efficiency Pulse Frequency Modulation DC-DC buck converter, supplied with a battery voltage ranging from 1.8 V to 3.6 V.The radio is based on a Low-IF receiver architecture with the VCO at twice the RF frequency and on a direct-modulation transmitter through a 2-point injection fractional-N PLL and a class-D full-bridge switched PA.
The SoC infrastructure is split into ten power domains, with power switches distributed over multiple power grids. A smooth switching scheme is developed to prevent any drop of the LDOs when turning on/off the domains. Always-On analog blocks are developed to reach extremely low current figures. An optimized trade-off between high speed constraints during active mode and low leakage during state retention is obtained from a smart leveraging of High Vt and Thick Oxide MOS transistors and from a 0.8 – 1.2 V supply voltage scaling coupled with source biasing in SRAM.Ten reconfigurable power saving modes are defined to address a large scope of IoT applications. With 1590 KGates, the measured complete SoC current consumption seen from the battery is 280 nA in its deepest power down mode (w/o retention), <1 µA with 4 KB SRAM retention.