RF-sampling DACs and ADCs integrated in 16nm FinFet SoCs

The need for high performance RF sampling data conversion has driven impressive developments of Current-Steering DACs and Pipelined SAR ADCs supported by time-interleaving and multiple calibration loops to maximize process portability and reduce cost, power and noise. Full integration of data converters into Digital RF SoCs enables great reductions of I/O power reduction, PCB area and BOM. However, SOC’s digital noise forces stringent isolation/crosstalk requirements to silicon, packaging and board level design and integration of high performance converters. DAC/ADC design challenges will be discussed by Bruno Vaz, while digital I/O challenges will be discussed by Christophe Erdmann.