Prediction and Mitigation of Spurs and Phase Noise in Fractional Synthesizers

Fractional synthesis promises high PFD rates, and thus low phase noise and fast tuning times – but is plagued by spurs and ‘unexpected’ noise degradation. Efficient prediction and modelling of these problems is more art than science. The proffered approach is to ‘divide and conquer’. Imperfections to the signal path include pushing due to coupling, supply interactions, memory effects, non-linearity, etc. The block level sensitivities are separately characterized in small setups, and then the aggression levels are estimated from higher level modelling of the supplies, package and electromagnetics. Optimization ensues to reduce sensitivity, aggression and coupling. In a fractional synthesizer, the feedback divider only produces discrete output phases (@ multiples of the VCO), but in closed loop, it exercises the PFD across a continuous range (See Figure 1). The dynamics of how it tap-dances across the range are influenced by the delta-sigma modulator (DSM) style and code. The DSM is often blamed as the source of spurs, but 1st order analysis shows it needs lots of help to be responsible. What is true, is that for the quantization noise to be properly shaped, a ‘+2’ code is expected to have exactly twice the effect as a ‘+1’ code, etc. If it doesn’t, the error charge goes somewhere – depending on the shape of the distortions and how they are exercised vs time, the error may be shaped, show up as a spur, as a white error source or some combination. The errors in Figure 1 are shown as lumped into a static charge-pump like transfer function, but they don’t have to be. In truth, one could visualize this transfer function as a dynamic entity that breaths and walks with various coupling mechanisms. One powerful way to attack these problems is to “reduce-the-spikey’s” –going through the design to down-size devices to the minimum and reduce ?I/ ?t. In one design, going to custom logic (instead of standard cells) brought 3x less power consumption of the delta-sigma, but far more importantly, reduced the peak currents (and thus aggression) by 10x. Figure 2 shows the result of some of these efforts - walking the output frequency in 100kHz steps across the band and plotting the worst visible spur on each channel on one of our early synthesizers vs one of the later offerings. The worst case spurs are about 25dB better, and more importantly there are clean and predictable regions – making frequency planning feasible.