Linearity, bandwidth, and back-off efficiency enhancement design techniques for GHz digitally intensive CMOS power amplifiers
Modern wireless systems often require multi-band and multi-mode operations to support various communication standards. At the same time, the widely employed spectrum-efficient modulation signals, such as 64 QAM and 256 QAM, often present large peak-to-average power ratio (PAPR). These have posed tremendous design challenges for the next-generation radio frequency (RF) power amplifier in terms of the RF carrier bandwidth, modulation bandwidth, amplitude (AM) and phase (PM) linearity, output power, power efficiency, and power back-off efficiency. This workshop presents various CMOS digitally intensive power amplifier architectures to achieve deep power back-off efficiency enhancement and inherent phase non-linearity and support high speed modulations. In addition, we will present the PA output passive network design techniques to achieve wide RF carrier bandwidth and to minimize the large-signal phase distortion of the power amplifier.