The complexity of physical circuit design is increasing with downscaling of CMOS technologies. In nanoscale FDSOI CMOS, it is not uncommon to battle with more than 5000 design rules. Pre-tapeout verification used to take weeks only. With DFM and other effects, and tool feedback available only after post layout extraction, the pre-tapeout phase can be several months. As a consequence many attempts to automate analog layout have been made over the years. This talk presents a compiler for automated layout of Analog-to-digital Converters (ADCS) that is based on layout regularity and a low number of unit devices. The input to the compiler is in text format and is split into three files: a SPICE netlist, an object definition file and a design rule file. Measured results of two compiled SAR-ADCs in 28nm FDSOI show state-of-the-art performance.