Performance of V-Band On-Chip Antennas in GlobalFoundries 45nm CMOS SOI Process for mm-Wave 5G Applications
This paper reports the performance of multiple V-band on-chip antennas implemented in Globalfoundries 45nm CMOS SOI process with high-resistivity substrate option. Dipole, slot and loop antennas are implemented as proof-of-concept designs. The antenna samples are flip-chip packaged on a PCB for testing. After de-embedding the loss from the feeding/matching network, the measured boresight antenna gains of the dipole, slot and loop are 3.9dBi, 3.8dBi and 3.7dBi, respectively, matching well with the 3D EM simulations. The measured radiation efficiencies are greater than 79% for all the three cases. Compared to other on-chip/on-package mm-Wave antennas, the demonstrated antennas are fully integrated in CMOS SOI process and do not require any post-processing, substrate-thinning/etching, lossy chip-to-package interconnections, or silicon lenses. It is demonstrated that the high-resistivity substrate option in Globalfoundries 45nm CMOS SOI technology is an effective solution to support high-efficiency and high-performance mm-Wave on-chip antennas, which paves the way for highly integrated mm-Wave transceiver systems including 5G phased arrays and massive MIMO systems.