An Ultra-Low-Power, High Gain Mixer for Smart Cities Applications
A high gain, ultra-low-power mixer in 45 nm standard CMOS process is presented. The mixer is designed by using coupling capacitors across drain-gate of the transconductance stages. The proposed mixer achieves a conversion gain of 18.5 dB and noise-figure of 19.2 dB at LO power of 0 dBm. The mixer achieves 14.5 dBm IIP3 and -16.2 dB P1dB for RF signal of 5.9 GHz. Operating at 0.4 V supply, the mixer consumes 170 µW power for RF frequencies of 2.4–5.9 GHz. The layout area of mixer core is 0.0046 mm². Post-layout simulations demonstrate that the proposed design achieves a very high figure-of-merit when compared to other state-of-the-art down-conversion CMOS mixers.