Digitally-Assisted Doherty Power Amplifier: Efficiency Enhancement and Linearity Improvement

This paper proposes a new digitally assisted Doherty Power Amplifier (PA) architecture that results in improved efficiency enhancement and linearity over conventionally linearized Doherty PAs. The improved adjustment of the phase delay between Main PA and Auxiliary PA, and thresholding of the Auxiliary PA waveform yields higher efficiency, but results in degraded linearity. This paper proposes a novel scheme of segmented digital predistortion (DPD) architecture that significantly improves the linearity of the PA in presence of these additional non-linearities. For validation, a symmetric LDMOS Doherty PA of ~57 dBm (500W) peak power, operating at center frequency of 1845MHz is used. With a stringent benchmark of -55dBc linearity requirement, a combined efficiency improvement of ~4 percentage points is achieved resulting from improved phase adjustment (~1.9%), and thresholding of the Auxiliary PA waveform (2.1%). Using a 2c-LTE10MHz test signal with an instantaneous bandwidth (IBW) of 40MHz, linearity improvement of ~11 dB is achieved with the segmented DPD architecture in comparison to conventional DPD approach of similar complexity.