Ruggedness Characterization of Bonding Wire Arrays in LDMOSFET-Based Power Amplifiers

Electro-thermo-stress (ETS) failure of bonding wire array in drain side of LDMOSFET based power amplifier during its high power’s ruggedness experiment is investigated in this paper. The temperature distribution of the LDMOSFET die surface and bonding wire array is also captured by a thermal infrared scanner. The temperature distribution is closely related to the profiles of the bonding wire array. Numerical methods are employed to calculate the bonding wire array, and the temperature distributions are demonstrated by using our finite element method (FEM) code. The simulated thermal results agree well with the testing results. Finally, an improved LDMOS design in optimizing the bonding wire profile is proposed. This research may serve as a guide for the design of a discrete LDMOS PA with improved reliability.