Analog-to-Digital Converter Architecture for Low-power and High-speed operation in Emerging Wireless Systems
There are increasing interests in widening the ADC bandwidth (hundreds MHz to GHz) while maintaining a sufficiently high resolution (>10bit) in emerging wireless systems. In this talk, we will overview the trend of ADC architecture explorations that attempt to address this emerging operation regime. Moreover, a massive time interleaving is typically exploited in this type of ADC. We will examine the various design challenges in such an ADC design, and the opportunities that the design community can continue to advance the state of the arts.