High Performance Frequency Synthesis with Digital Calibration Techniques
Frequency synthesis is driven by ever increasing system requirements such as low cost (e.g. for IoT applications), low power (e.g., for mobile devices), low phase noise (e.g., for wideband modulations) and multi-phase outputs (e.g., for N-path filtering and passive-mixing). Digital phase locked loops (DPLLs) have advantages of high flexibility for digital calibration that can be utilized to compensate the imperfectness of analog circuits due to mismatches and process-voltage-temperature (PVT) variations. Calibration is essential for achieving superior linearity of time-to-digital converters and digitally controlled oscillators, which in return greatly affects the output spectral purity such as fractional spurious tones. Improving synthesizer spectral purity is normally obtained at the price of higher power consumption. We will discuss the techniques to break this trade-off by both circuit and architectural innovations. This talk will also addresses the design challenges in emerging frequency synthesis techniques such as sub-sampling and injection-locking and the roles digital calibration plays for the improvement of their performances.