Exploiting Digital Friendly CMOS Power Amplifiers and Systems for 5G Communications
CMOS is ubiquitous for computation, and as such plays an ever increasing role in our lives as we use computation to improve working efficiency. Increasing levels of integration have made it possible to embed analog and RF circuits with digital processing to create RF systems-on-chip. In this talk we will introduce a few digital friendly transmitter techniques (e.g., SCPA, R-DAC, and I-DAC). Digital friendly architectures are linear and efficient in relatively deep power back off, but as yet have not shown significant operation beyond 10 GHz. Such architectures are strong in S and C band, and methods to expand their operating frequency range will be discussed. Their operation in 5G networks is likely, as massive MIMO will reduce the need for high output power per radiating element and instead will use coordination of many (>100) lower power radiating elements. In addition to digital friendly architectures, we will present a few systems that are friendly for hybrid integration with III-V, GaN and SiGe transistors.