High-Performance CMOS Frequency Synthesizer for WLAN Applications
In this presentation, several key circuit techniques for both analog and digital architectures will be introduced to improve both jitter and power consumption for WLAN and WPAN applications. A pulse-tail-feedback VCO is promising for lowering flicker noise in oscillators, which achieves FoM of 195dBc/Hz with flicker noise corner of 700Hz. A fractional-N Sub-sampling PLL using a pipelined phase interpolator and DTC will be presented. The phase interpolator mitigates DTC range and contributes to linearity improvement, and -59dBc worst-case fractional spur is achieved. For AD-PLL, a highly-linear and low-power DTC and TDC will be presented as well as linearity calibration techniques. An isolated constant-slope DTC realizes 10bit 0.1mW operation with 26MHz reference clock, and sub-ps INL is achieved. The DTC-based AD-PLL achieves FoM of -246dB with -56 worst-case fractional spur. Finally, a carrier-frequency scaling issue will be explained for future wireless system.